Systolic RNS arithmetic using feedback shift logic

The author presents an alternative architecture for the arithmetic units in pipelined residue-number-system applications. This architecture uses feedback shift logic to implement residue adders and multipliers, together with novel data representations derived from the multiplicative group of finite rings. Each stage can be implemented with only one exclusive-OR delay. Thus this architecture shows promise in increasing the throughput of residue arithmetic units over conventional logic and ROM (read-only memory) designs.<>