DocumentCode :
2425284
Title :
Easing the verification bottleneck using high level synthesis
Author :
Varma, Devadas ; Mackay, Duncan ; Thiruchelvam, Pradeep
Author_Institution :
AutoESL Design Technol., Cupertino, CA, USA
fYear :
2010
fDate :
19-22 April 2010
Firstpage :
253
Lastpage :
254
Abstract :
As design size grows, the verification complexity grows along with the size of the design description. When design descriptions are written in RTL, the complexity of the testbenches to test this RTL are enormous. As more and more design entry moves to higher level languages such as C/C++ and System C, it´s possible to write testbenches in C to verify the functionality of these high level models. However, for design implementation, an RTL description is still required. If this RTL is written by hand, most of the advantages of creating a high-level description evaporate, as the RTL has still to be re-verified using a testbench at the RT level of abstraction. Besides offering the many advantages of automated synthesis, ease of architecture exploration, ability to make complex architectural changes like pipelining, resource sharing and scheduling automatically, perhaps the most important time saver offered by HLS is its ability to make RTL verification easier. In this paper we show how AutoPilot, a new generation of HLS tool from AutoESL, makes the task of generating and verifying RTL descriptions of designs from C based languages easier. We show you how you can use C testbenches to verify the functionality of C-based designs at high abstraction levels several orders of magnitude faster than traditional RT level verification. Then with AutoPilot synthesis, quickly generate several implementations of this design in RTL, optimized for different area, timing and power constraints, and use the same testbench already used to verify the C design description, to automatically verify the generated RTL implementations. The automatic reuse of the C testbench and the significant reduction in the verification time also allows designers to accommodate changes in design specification without impacting schedule. Along with the use of other technologies such as code coverage tools and formal verification, this flow offers a substantial improvement to methodologies based on RTL alone.
Keywords :
C language; circuit complexity; formal specification; formal verification; high level synthesis; scheduling; AutoPilot; C based languages; C-based design functionality; C/C++; HLS tool; RTL description; System C; design description; formal verification; high level synthesis; power constraints; scheduling; verification complexity; Automatic testing; Constraint optimization; Design optimization; Formal verification; High level synthesis; Pipeline processing; Power generation; Resource management; System testing; Timing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
VLSI Test Symposium (VTS), 2010 28th
Conference_Location :
Santa Cruz, CA
ISSN :
1093-0167
Print_ISBN :
978-1-4244-6649-8
Type :
conf
DOI :
10.1109/VTS.2010.5469565
Filename :
5469565
Link To Document :
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