A parallel unification coprocessor

Author

Sibai, F.N. ; Watson, K.L. ; Lu, Mi

Author_Institution

Dept. of Electr. Eng., Texas A&M Univ., College Station, TX, USA

fYear

1989

fDate

23-25 Oct 1989

Firstpage

608

Lastpage

615

Abstract

A parallel unification coprocessor partitioning unification into a match step and a consistency check step and conducting these two steps concurrently in a pipeline fashion is presented. The machine´s architecture, algorithm, and processors are described. The machine is simulated at the register transfer level, and the simulation results as well as performance comparisons with two serial unification coprocessors are presented. The parallel unification coprocessor with only two MPs (match processors) was shown to be significantly faster than the two serial coprocessors for compound terms of arities higher than two. The study of the unification of long terms indicated that the coprocessor reaches its peak performance with 3 MPs in most cases. This seems to confirm that the cost of the fourth MP is not justified, and therefore it seems that only three MPs will be needed in the future

Keywords

logic programming; parallel machines; performance evaluation; pipeline processing; special purpose computers; consistency check step; match processors; match step; parallel unification coprocessor; peak performance; register transfer level; serial unification coprocessors; simulation results; Application software; Artificial intelligence; Computational modeling; Coprocessors; Expert systems; Learning; Logic programming; Pattern matching; Registers; Speech;

fLanguage

English

Publisher

ieee

Conference_Titel

Tools for Artificial Intelligence, 1989. Architectures, Languages and Algorithms, IEEE International Workshop on

Conference_Location

Fairfax, VA

Print_ISBN

0-8186-1984-8

Type

conf

DOI

10.1109/TAI.1989.65374

Filename

65374