Innovative practices session 7C: Verification and testing challenges in high-level synthesis

Recent years have seen continuing miniaturization of VLSI technologies, producing chips with very high transistor density. A consequence of this advancement, together with high computational demands of modern applications, is that hardware designs are rising in complexity to make use of all the available transistors. This makes it challenging to develop reliable hardware through hand-crafted RTL implementations. The problem is exacerbated with aggressive time-to-market requirements, leading to a design productivity gap. Electronic System Level (ESL) design is often seen as a solution to this gap: the idea is to raise the design abstraction by specifying a hardware design behaviorally with a high-level language (e.g., SystemC). High-level synthesis translates ESL specifications to RTL, through several inter-dependent transformations (e.g., compilation, scheduling, resource allocation, control synthesis, etc).