DocumentCode :
2425386
Title :
Board-level fault diagnosis using Bayesian inference
Author :
Zhang, Zhaobo ; Wang, Zhanglei ; Gu, Xinli ; Chakrabarty, Krishnendu
Author_Institution :
ECE Dept., Duke Univ., Durham, NC, USA
fYear :
2010
fDate :
19-22 April 2010
Firstpage :
244
Lastpage :
249
Abstract :
Increasing integration densities and high operating speeds are leading to subtle manifestations of defects at the board level. Board-level functional test is therefore necessary for product qualification. The diagnosis of functional failures is especially challenging, and the cost associated with board-level diagnosis is escalating rapidly. An effective and cost-efficient board-level diagnosis strategy is needed to reduce manufacturing cost and time-to-market, as well as to improve product quality. In this paper, we use Bayesian inference to develop a new board-level diagnosis framework that allows us to identify faulty devices or faulty modules within a device on a failing board with high confidence. Bayesian inference offers a powerful probabilistic method for pattern analysis, classification, and decision making under uncertainty. We apply this inference technique by first generating a database of fault syndromes obtained using fault-insertion test at the module pin level on a fault-free board, and then use this database along with the observed erroneous behavior of a failing board to infer the most likely faulty device. Results on a case study using an open-source RISC system-on-chip highlight the effectiveness of the proposed framework in terms of fault-localization accuracy and correctness of diagnosis.
Keywords :
decision making; electronic engineering computing; fault diagnosis; inference mechanisms; integrated circuit testing; reduced instruction set computing; system-on-chip; Bayesian inference; board-level diagnosis; board-level fault diagnosis; board-level functional test; decision making; fault-insertion test; fault-localization accuracy; open-source RISC system-on-chip; pattern analysis; pattern classification; probabilistic method; product qualification; product quality; time-to-market; Bayesian methods; Cost function; Databases; Decision making; Fault diagnosis; Manufacturing; Pattern analysis; Qualifications; Testing; Time to market;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
VLSI Test Symposium (VTS), 2010 28th
Conference_Location :
Santa Cruz, CA
ISSN :
1093-0167
Print_ISBN :
978-1-4244-6649-8
Type :
conf
DOI :
10.1109/VTS.2010.5469569
Filename :
5469569
Link To Document :
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