DocumentCode :
2425647
Title :
At-speed scan test with low switching activity
Author :
Moghaddam, Elham K. ; Rajski, Janusz ; Kassab, Mark ; Reddy, Sudhakar M.
Author_Institution :
Dept. of ECE, Univ. of Iowa, Iowa City, IA, USA
fYear :
2010
fDate :
19-22 April 2010
Firstpage :
177
Lastpage :
182
Abstract :
This paper presents a novel method to generate test vectors that mimic functional operation from switching activity point of view. The method uses states obtained by applying a number of functional clock cycles starting from the scan-in state of a test vector to fill the unspecified scan cell values in test cubes. Experimental results presented for industrial circuits demonstrate the effectiveness of the proposed method.
Keywords :
automatic test pattern generation; integrated circuit testing; at-speed scan test; functional clock cycles; industrial circuits; switching activity; test vector generation; Circuit testing; Cities and towns; Clocks; Fault detection; Graphics; Hamming distance; Law; Legal factors; Sequential analysis; Very large scale integration; At-speed test; IR-drop; Low power tests; Switching activity; scan design;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
VLSI Test Symposium (VTS), 2010 28th
Conference_Location :
Santa Cruz, CA
ISSN :
1093-0167
Print_ISBN :
978-1-4244-6649-8
Type :
conf
DOI :
10.1109/VTS.2010.5469580
Filename :
5469580
Link To Document :
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