Low power compression architecture

DFT Compression and limiting power during test are two of the recent active areas of interest in the domain of DFT and Manufacturing Test. Many of the low-power test techniques, as well as DFT compression schemes exploit the `don´t-care´ bits in ATPG vectors to achieve the desirable results, and hence often can be in conflict with each other. In this paper, we show how we can alter a commonly known DFT compression scheme - Illinois-Scan-Chain design, also known as Broadcast-Scan, for low power test. Results show the effectiveness of the proposed DFT Compression scheme in reducing switching power during test.