Title :
Scalable and accurate estimation of probabilistic behavior in sequential circuits
Author :
Yu, Chien-Chih ; Hayes, John P.
Author_Institution :
Dept. of Electr. Eng. & Comput. Sci., Univ. of Michigan, Ann Arbor, MI, USA
Abstract :
We present a new methodology for fast and accurate simulation of signal probabilities in sequential logic. It can be used for analyzing soft error effects at the logic level, estimating circuit reliability, and the like. Experimental results for large benchmarks show that signal error probabilities can be estimated over many cycles with high accuracy.
Keywords :
VLSI; integrated circuit reliability; probability; sequential circuits; VLSI; circuit reliability; logic level; scalable accurate estimation; sequential circuits; sequential logic; signal error probabilities; soft error effects; Circuit simulation; Circuit testing; Clocks; Computational modeling; Error probability; Logic circuits; Logic testing; Probabilistic logic; Sequential circuits; Voltage; sequential circuits; signal probability estimation; simulation methods; soft error models;
Conference_Titel :
VLSI Test Symposium (VTS), 2010 28th
Conference_Location :
Santa Cruz, CA
Print_ISBN :
978-1-4244-6649-8
DOI :
10.1109/VTS.2010.5469586
