Innovative practices session 5C: Post-silicon debug

Despite advances in design and pre-silicon verification, it is becoming increasingly common for postsilicon validation to discover design errors as well as serious marginalities which threaten a design´s economic viability. Consequently, increasingly chip designs are undergoing multiple silicon spins. This is the case not only for high-performance custom and semi-custom chips but also for ASICs. For example, Collett International Research reports that 37% of ASICs require a second spin while 24% of ASICs require more than two spins. Post-silicon validation is hence assuming an increasingly central role in the development of high-performance chips. In this session, we have invited industrial experts in post-silicon validation to share their experiences. In particular, they will share their approach for improving the quality of validation methodology to ensure detection of all possible serious causes of circuit misbehavior which threaten a chip´s economic viability. They will also share their experience with diagnosis for identifying underlying root causes to facilitate rapid redesign. They will touch upon how post-silicon validation helps improve our understanding of new processes and facilitates process and design improvements. The invited experts will cover a wide range of high-end designs, including multi-core microprocessors, high-performance special-purpose processors, as well as memory-intensive chips including SoCs.