Theoretical analysis for low-power test decompression using test-slice duplication

This paper presents a single-test-input test-decompression scheme, named STSD, which utilize the technique of test-slice duplication to reduce the test-data volume as well as the signal transitions along scan paths. The encoding of STSD scheme focuses on maximizing the number of duplications made by a test-slice template. Mathematical models are also developed in this paper to estimate the compression ratio, test-application time, and scan-in transitions caused by STSD scheme, and in turn can further help designers to efficiently identify the best configuration of STSD scheme instead of going through a time-consuming simulation process. The experimental results based on large ISCAS and ITC benchmark circuits demonstrate the accuracy of the proposed mathematical models and the advantages of using STSD scheme.