Localization of SILC in flash memories after program/erase cycling

This work shows a new technique for localizing the position of the weak site responsible for the stress-induced leakage current (SILC) in the tunnel oxide of flash memories. Reverse biasing the drain-substrate junction during gate-stress results in local modification of the electric field through the oxide, leading to a corresponding change in the local leakage current. Our analysis on selected samples of flash cells indicates that the SILC-related damage can be partly localized close to the gate-to-drain overlap, indicating that the hot-carrier programming cooperates in the degradation process.