DocumentCode
2426113
Title
Multiblock RAM Access Controller IP cores generator
Author
Dunets, Bohdan
Author_Institution
Comput. Eng. Dept., Lviv Polytech. Nat. Univ., Ukraine
fYear
2003
fDate
18-22 Feb. 2003
Firstpage
214
Lastpage
215
Abstract
Paper introduces a Multiblock RAM Access Controller architecture, which makes possible high-bandwidth, conflict-less access from initiators to RAM blocks. Requests are processed in order for each requester with fixed processing time using original read-write ahead scheduling algorithm.
Keywords
DRAM chips; authorisation; hardware description languages; hardware-software codesign; microcontrollers; shared memory systems; storage management chips; system-on-chip; IP cores generator; RAM blocks; VHDL-model; fixed processing time; high-bandwidth conflictless access; multiblock RAM access controller; multiport memory; read-write ahead scheduling algorithm; register-transfer-level controller; shared memory multiprocessor; system-on-chip; Bandwidth; Costs; Multiprocessing systems; Quality of service; Random access memory; Read-write memory; Scheduling algorithm; Sorting; System-on-a-chip; Writing;
fLanguage
English
Publisher
ieee
Conference_Titel
CAD Systems in Microelectronics, 2003. CADSM 2003. Proceedings of the 7th International Conference. The Experience of Designing and Application of
Print_ISBN
966-553-278-2
Type
conf
DOI
10.1109/CADSM.2003.1255035
Filename
1255035
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