On-the-fly variation tolerant mapping in crossbar nano-architectures

In hybrid nano-architectures, self-assembled nanoscale crossbars are fabricated on top of a reliable CMOS subsystem. Bottom-up self-assembly nanofabrication process, used in nano-architectures, yields nanodevices with significantly more variations compared to the conventional top-down lithography used in CMOS fabrication. This is in addition to an increased defect density expected for self-assembled nanodevices. Therefore, it is one of the major design challenges to tolerate variation and defects in emerging nano architectures. In this paper, we present an alternative approach for variation and defect tolerant mapping in which no application-independent test and characterization (defect and variation map) is required. The variation tolerant mapping is done on-the-fly which can ultimately be transformed into built-in self-mapping. Different mapping algorithms are presented and their efficiencies in terms of variation and defect tolerance as well as mapping time are compared. The experimental results show that the proposed heuristic mapping algorithm can achieve the same success rate with the exhaustive method in terms of meeting required timing constraints with orders of magnitude fewer reconfiguration retries.