Title :
Gate-oxide early-life failure identification using delay shifts
Author :
Kim, Young Moon ; Chen, Tze Wee ; Kameda, Yoshio ; Mizuno, Masayuki ; Mitra, Subhasish
Author_Institution :
Dept. of Electr. Eng., Stanford Univ., Stanford, CA, USA
Abstract :
This paper presents experimental data from digital circuits on 90nm test chips, together with circuit simulations, to establish the following results: 1. The presence of a gate-oxide early-life failure (ELF) candidate transistor (also called infant mortality) in a logic gate results in delay shifts over time; 2. Delay shifts can be effective indicators of gate-oxide ELF suspects that may be detected using inexpensive digital techniques. These results can be utilized to overcome scaled-CMOS reliability challenges through effective ELF screening during production test or on-line during system operation for systems with built-in self-healing.
Keywords :
CMOS logic circuits; built-in self test; circuit simulation; delay circuits; failure analysis; integrated circuit reliability; logic testing; ELF screening; built-in self-healing; circuit simulations; delay shifts over time; digital circuits; digital techniques; gate-oxide early-life failure identification; infant mortality; logic gate; production test; scaled-CMOS reliability; size 90 nm; system operation; Automatic testing; Circuit simulation; Circuit testing; Delay effects; Digital circuits; Geophysical measurement techniques; Ground penetrating radar; Logic gates; Production systems; System testing;
Conference_Titel :
VLSI Test Symposium (VTS), 2010 28th
Conference_Location :
Santa Cruz, CA
Print_ISBN :
978-1-4244-6649-8
DOI :
10.1109/VTS.2010.5469615