Title :
Forming multi-cycle tests for delay faults by concatenating broadside tests
Author :
Pomeranz, Irith ; Reddy, Sudhakar M.
Author_Institution :
Sch. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA
Abstract :
A multi-cycle (or multi-pattern) scan-based test consists of several primary input patterns, which are applied consecutively in functional mode, between scan operations. Multi-cycle tests can reduce the total number of cycles needed to achieve a target fault coverage. Additionally, such tests exercise the circuit in its functional mode of operation during several clock cycles where the primary input patterns are applied. This is important for detecting defects that are not detected with two-pattern scan-based tests. However, a complete test generation process for multi-pattern tests requires sequential test generation. To generate multi-pattern tests with arbitrary numbers of patterns without performing full sequential test generation, and targeting delay faults, we use a broadside test set as a basis for test generation. We introduce the operation of concatenating broadside tests, and describe a procedure that uses it to form multi-cycle tests. We present experimental results demonstrating that the test sets require significantly fewer test cycles than broadside test sets, for the same transition fault coverage.
Keywords :
automatic test pattern generation; delays; fault diagnosis; integrated circuit testing; concatenating broadside tests; delay faults; functional testing mode; multicycle scan-based test; multipattern tests; sequential test generation; test generation process; Circuit faults; Circuit testing; Cities and towns; Clocks; Delay; Performance evaluation; Sequential analysis; Signal generators; Test pattern generators; Very large scale integration; broadside tests; multi-cycle tests; scan circuits; transition faults;
Conference_Titel :
VLSI Test Symposium (VTS), 2010 28th
Conference_Location :
Santa Cruz, CA
Print_ISBN :
978-1-4244-6649-8
DOI :
10.1109/VTS.2010.5469616