Title :
Low cost test and tuning of RF circuits and systems
Author :
Chatterjee, Avhishek ; Taenzler, Friedrich
Author_Institution :
Georgia Tech, Atlanta, GA, USA
Abstract :
Summary form only given. The demand for multi-faceted wireless applications has led to increased levels of device integration and migration of RF to CMOS technologies. However, the resulting circuits are increasingly susceptible to manufacturing process variations, coupled noise (substrate, power planes) from onchip digital signal processing circuitry, thermal fluctuations (Vt sensitivity to temperature), resulting mismatch effects and device wear-out (Vt degradation) phenomena. In the recent past, "alternative" testing methods have been used to perform parametric testing of RF transceivers.. These allow simple tests to measure complex RF specifications while at the same time allowing catastrophic failures to be detected. All (or most) of the device under test (DUT) specifications are evaluated from a single test application which may be repeated multiple times to average out noise effects.
Keywords :
CMOS integrated circuits; digital signal processing chips; manufacturing processes; radiofrequency integrated circuits; transceivers; CMOS technology; RF circuits; RF transceivers; alternative testing methods; catastrophic failures; coupled noise; device integration; device under test specifications; device wear-out phenomena; manufacturing process variations; mismatch effects; multifaceted wireless applications; noise effects; onchip digital signal processing circuitry; parametric testing; thermal fluctuations; CMOS technology; Circuit optimization; Circuit testing; Circuits and systems; Costs; Coupling circuits; Manufacturing processes; Radio frequency; System testing; Wireless sensor networks;
Conference_Titel :
VLSI Test Symposium (VTS), 2010 28th
Conference_Location :
Santa Cruz, CA
Print_ISBN :
978-1-4244-6649-8
DOI :
10.1109/VTS.2010.5469621