Structural analysis for digital devices for the simulation system

Author

Hahanov, Vladimir ; Yegorov, A. ; Obrizan, Vladimir ; Parfentiy, Alexander

Author_Institution

Comput.-Aided Design Dept., Kharkov Nat. Univ of Radioelectronics, Ukraine

fYear

2003

fDate

18-22 Feb. 2003

Firstpage

264

Lastpage

268

Abstract

Fast algorithms for structural analysis of large digital devices containing millions of equivalent gates are offered. These algorithms are used in the preprocessing stage for increase of fault simulation and test generation speed. The data structures and program procedures for algorithm realization are described. The ATPG system is offered.

Keywords

automatic test pattern generation; circuit CAD; circuit simulation; data structures; fault simulation; field programmable gate arrays; integrated circuit testing; logic CAD; logic testing; programmable logic devices; ATPG system; CPLD; FPGA; algorithms realization; data structures; digital devices; equivalent gates; fast structural analysis algorithms; fault simulation; program procedures; simulation system; structural analysis; test generation speed; Algorithm design and analysis; Analytical models; Automatic testing; Circuit faults; Circuit simulation; Circuit testing; Computational modeling; Digital circuits; Digital systems; System testing;

fLanguage

English

Publisher

ieee

Conference_Titel

CAD Systems in Microelectronics, 2003. CADSM 2003. Proceedings of the 7th International Conference. The Experience of Designing and Application of

Print_ISBN

966-553-278-2

Type

conf

DOI

10.1109/CADSM.2003.1255056

Filename

1255056