Title :
ESD circuit simulation for the prevention of ESD failures - application to products in a 0.18 μm CMOS technology
Author :
Wolf, Heinrich ; Gieser, Horst
Author_Institution :
Fraunhofer-Inst. Zuverlassigkeit und Mikrointegration, Munich, Germany
Abstract :
This paper describes the ESD circuit simulation of MOS transistors processed in a 0.18 μm CMOS technology. The extended model simulates the breakdown between the external base and the emitter diffusion as well as the forward bias condition. The applied parameter extraction methodology also comprises device simulation. Including the transient behavior the model is verified by means of test circuits. Moreover, this approach simulates "real world" failures of product circuits.
Keywords :
CMOS integrated circuits; MOSFET; circuit simulation; electric breakdown; electrostatic discharge; failure analysis; integrated circuit modelling; 0.18 micron; CMOS technology; ESD circuit simulation; ESD failure; MOS transistor; electric breakdown; parameter extraction; CMOS process; CMOS technology; Circuit simulation; Circuit testing; Coupling circuits; Electric breakdown; Electrostatic discharge; MOSFETs; Parameter extraction; Semiconductor device modeling;
Conference_Titel :
Reliability Physics Symposium Proceedings, 2002. 40th Annual
Print_ISBN :
0-7803-7352-9
DOI :
10.1109/RELPHY.2002.996630
