Establishing ASIC fault-coverage guidelines for high-reliability systems

Electronic systems are being designed with increasing levels of digital logic integration, quite often in the form of digital application specific integrated circuits (ASICs). The level of integration in these devices (10000 to greater than 100000 primitive logic elements such as “gates” and/or flip flops) presents a difficult challenge to design engineers for the development of a comprehensive set of test vectors to verify that all of the elements within the ASIC operate correctly. The percentage of possible logic elements (gates, flip flops, etc.) tested by the test vectors is known as fault coverage (FC). Although 100% fault coverage is a desired goal, quite often the complexity of the ASICs preclude reaching that goal. The hazards of insufficient fault coverage are magnified in complex systems with many ASICs, for if an untested defective logic element were to be exercised in any one ASIC, a system failure would occur. This paper presents a mathematical model to develop digital ASIC fault coverage guidelines for complex electronic systems. The model is based on established probabilistic relationships between integrated circuit fabrication yields, fault coverage and the resulting device defect level, combined with an estimated probability that untested logic elements will be exercised in use. The results of this model can be used to allocate the ASIC fault coverage requirements necessary to achieve high system mission success rates