Title :
Automatic generation of memory built-in self-repair circuits in SOCs for minimizing test time and area cost
Author :
Tseng, Tsu-Wei ; Hou, Chih-Sheng ; Li, Jin-Fu
Author_Institution :
Dept. of Electr. Eng., Nat. Central Univ., Jhongli, Taiwan
Abstract :
Built-in self-repair (BISR) techniques are widely used to enhance the yield of memories in a system-on-chip (SOC). A SOC typically consists of hundreds of memories. Cost-efficient BISR schemes for repairing those memories thus are imperative. In this paper, we propose a memory BISR automatic generation (MBAG) framework for designing memory BISR circuits in a SOC. The MBAG framework consists of a test scheduling engine and a memory grouping engine for the minimization of test time and area cost of the BISR circuits. The test scheduling algorithm has been presented in our previous work [1]. In this paper, therefore, we focus on the introduction of the grouping algorithm determining the memories which can share a BISR circuit under the constraints of distance and scheduling results. Simulation results show that the proposed MBAG can generate reconfigurable BISR circuits for 20 memories such that 50% area reduction is achieved in comparison with a dedicated BISR scheme if the distance constraint is 3mm and the test power constraint is 80mW.
Keywords :
automatic test pattern generation; integrated circuit design; integrated circuit testing; integrated circuit yield; semiconductor storage; system-on-chip; SOC; area cost; grouping algorithm; memory built-in self-repair circuit automatic generation; memory grouping engine; system-on-chip memory; test scheduling algorithm; test scheduling engine; test time; Automatic testing; Built-in self-test; Circuit testing; Costs; Engines; Minimization; Power generation; Scheduling algorithm; System testing; System-on-a-chip;
Conference_Titel :
VLSI Test Symposium (VTS), 2010 28th
Conference_Location :
Santa Cruz, CA
Print_ISBN :
978-1-4244-6649-8
DOI :
10.1109/VTS.2010.5469627