A compact three-step pipelined CMOS current-mode A/D converter

This paper describes the architecture and circuit design of a three-step pipelined A/D converter implemented using the continuous-time current-mode technique. A transistor-only three-step architecture was used to optimize area and power dissipation while maintaining analog bandwidth and hence the effective number of bits over the full input Nyquist band. Simulation results show 8-bit accuracy with a sampling rate up to 54 MHz. The A/D converter is fabricated in a standard single poly double-metal digital 0.8 μm CMOS process and occupies a die area of 0.38 mm² including input current and reference pads. The entire circuit dissipates 20 mW at 54 MHz of conversion rate while operating from a single 5 V power supply