Multi-Objective Optimization Techniques for VLSI Placements

Floorplanning is a vital phase in the physical design process of very large scale integrated (VLSI) circuit. The main objective of floorplanning is to minimize chip area. In recent years, the integration density of VLSI is increasing and the size is becoming very small. Therefore, many factors such as the increase in the temperature of the chip and complexity of circuit design are should be solved. The increased temperature causes the quality degradation and reliability deterioration of a chip. The primary objective function for floorplanning is to minimize the total area of a chip. In this paper, we propose a multi-objective function considering temperature aware and dispersion of the module to minimize the chip area using the simulated annealing (SA). As a floorplan representation, we use single-sequence because it is simple and effective. The hotspot tool is used to obtain the temperature in the chip region by using the power density of each module and the dispersion of the module is used to consider the distances of each module from the center of the chip. The simulation results show that this multi-objective function can adjust the relationship between chip area and chip temperature to achieve required design.