Design and performance of a modular hardware process mapper (scheduler) for a real-time token controlled data driven multiprocessor architecture

Dynamic process mapping mechanisms can be responsible for efficient routing of control tokens through real-time data driven multiprocessor architectures. These mechanisms perform a resource allocation function within such an architecture and are therefore critical to the real-time operation and performance of such an architecture. Dynamic process mapping mechanisms can be realized in hardware or software. It can be shown a hardware process mapping mechanism is faster than a functionally equivalent software process mapper. This paper presents a fast dynamic modular hardware process mapping mechanism for a real-time data-driven multiprocessor architecture, the dynamic pipeline computer architecture (DPCA), its organization and design suitable for VLSI implementation and a performance analysis. The basic process mapper design is modular and therefore may be utilized in parallel data-driven computer architectures. Process mapping time is shown to be proportional to O[log ₂ N] where N represents the number of process mapping modules required within a token controlled data driven multiprocessor system