High voltage SOI P-channel field MOSFET structures

Author

Lu, David Hongfei ; Mizushima, Tomonori ; Sumida, Hitoshi ; Saito, Masaru ; Nakazawa, Haruo

Author_Institution

Electron Device Lab., Fuji Electr. Device Technol. Co. Ltd., Matsumoto, Japan

fYear

2009

fDate

14-18 June 2009

Firstpage

17

Lastpage

20

Abstract

We comparatively investigated the impact of layout and trench on four types of field oxide Pch MOSTs in a thick film SOI technology with due consideration to isolation trench. High blocking capability (~20 V per um of drift length) for both off- and on- state breakdown voltage close to 300 V, along with reasonable high temperature reverse bias ruggedness, has been experimentally realized with minimum overhead area by source-centered single trench structure in which the trench sidewall grounded.

Keywords

MOSFET; elemental semiconductors; isolation technology; semiconductor device breakdown; silicon; silicon-on-insulator; SOI P-channel field MOSFET structures; Si; field oxide Pch MOST; high blocking capability; high voltage; isolation trench; layout; minimum overhead area; off-state breakdown voltage; on-state breakdown voltage; source-centered single trench structure; thick film SOI technology; CMOS logic circuits; Electron devices; Integrated circuit technology; Isolation technology; Logic devices; MOSFET circuits; Plasma displays; Silicon on insulator technology; Thick films; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Power Semiconductor Devices & IC's, 2009. ISPSD 2009. 21st International Symposium on

Conference_Location

Barcelona

ISSN

1943-653X

Print_ISBN

978-1-4244-3525-8

Electronic_ISBN

1943-653X

Type

conf

DOI

10.1109/ISPSD.2009.5157990

Filename

5157990