Fault diagnosis in VLSI/WSI processor arrays

An efficient and application-independent fault diagnosis method in VLSI/WSI processor arrays is presented. Four selectors, two comparators, two registers, one latch, and one OR gate are added to each processing element (PE) in the array to make the array easily diagnosable. By applying functional test patterns to each PE in the array, multiple-PE failures can be detected and located. In the method, all the PEs perform self-comparison operations simultaneously. The self-comparison approach is applicable to any structure of PEs. The test pattern size is fixed regardless of the array size. Although the whole design is for a unidirectional two-dimensional processor array, the same methodology can be extended to other kinds of array structures. This approach is unique in the multiple fault diagnosis capability as well as high-fault coverage and small testing time. Switch and link faults as well as PE faults are included in the fault model