Reduced switching stress in high-voltage IGBT inverters via a three-level structure

Author

Brumsickle, William E. ; Divan, Deepak M. ; Lipo, TA

Author_Institution

Dept. of Electr. & Comput. Eng., Wisconsin Univ., Madison, WI, USA

Volume

2

fYear

1998

fDate

15-19 Feb 1998

Firstpage

544

Abstract

High voltage (3.3-4.5 kV) insulated gate bipolar transistors (HVIGBTs) are limited in SOA and ability to be effectively used in hard switched 2-level PWM inverters. The proposed operation sequence for the well known 3-level inverter allows use of HVIGBTs at near-rated voltage while cutting switching loss in half and allowing 3-level PWM for improved harmonics spectrum. Simulation and laboratory results prove the concept

Keywords

PWM invertors; harmonics; insulated gate bipolar transistors; losses; switching circuits; 3-level inverter; 3.3 to 4.5 kV; PWM inverters; harmonics spectrum improvement; high-voltage IGBT inverters; insulated gate bipolar transistors; operation sequence; reduced switching stress; switching loss reduction; three-level structure; Diodes; Insulated gate bipolar transistors; Pulse width modulation; Pulse width modulation inverters; Semiconductor optical amplifiers; Stress; Switches; Switching frequency; Switching loss; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Applied Power Electronics Conference and Exposition, 1998. APEC '98. Conference Proceedings 1998., Thirteenth Annual

Conference_Location

Anaheim, CA

Print_ISBN

0-7803-4340-9

Type

conf

DOI

10.1109/APEC.1998.653944

Filename

653944