Native mode functional self-test generation for Systems-on-Chip

With the rapid increase in the functionality of a single chip, the generation of high quality manufacturing tests which can be applied at-speed has become a serious issue. The problem is further compounded with an increasing level of integration in the case of Systems-On-Chip (SOCs), for which existing test generation tools are inadequate. Many of the peripherals in a SOC design may not include testability features, which renders conventional design for testability (DFT) approaches ineffective. Functional tests applied at-speed in the native mode of a microprocessor have been shown to be effective in detecting realistic defects. A novel approach to adopt this strategy to generate test patterns for SOCs is presented in this paper. This approach utilizes the core processor´s instruction set to test its own functionality and that of the peripheral components. A SOC based on a model of the Intel 8085 processor is used to show the effectiveness of this approach.