Title :
0.15µm BiC-DMOS technology with novel stepped-STI N-channel LDMOS
Author :
Yanagi, Shinichiro ; Kimura, H. ; Nitta, T. ; Kuroi, T. ; Hatasako, K. ; Maegawa, S. ; Onishi, K. ; Otsu, Y.
Author_Institution :
Renesas Technol. Corp., Itami, Japan
Abstract :
We developed a state-of-the-art BiC-DMOS process using 0.15 mum technology. High-voltage MOSFETs were embedded in our standard 0.15 mum CMOS process with a 0.13 mum high density NVM. More intelligent mixed signal devices can flexibly be realized by this technology. Moreover, the reliability of n-ch LDMOS is markedly improved by the novel structure of stepped-STI LDMOS.
Keywords :
CMOS integrated circuits; MOSFET; BiC-DMOS technology; CMOS; MOSFET; n-channel LDMOS; shallow trench isolation; CMOS logic circuits; CMOS process; CMOS technology; Degradation; Hot carrier injection; Impact ionization; Intrusion detection; Logic devices; Nonvolatile memory; Proximity effect;
Conference_Titel :
Power Semiconductor Devices & IC's, 2009. ISPSD 2009. 21st International Symposium on
Conference_Location :
Barcelona
Print_ISBN :
978-1-4244-3525-8
Electronic_ISBN :
1943-653X
DOI :
10.1109/ISPSD.2009.5158006
