DocumentCode
2429361
Title
Design of low emission integrated circuits
Author
Sicard, Etienne ; DELMAS BENDHIA, Sonia
Author_Institution
Dept. of Comput. & Electr. Eng., Inst. Nat. des Sci. Appliquees, Toulouse, France
fYear
2000
fDate
2000
Abstract
This paper describes a set of efficient design techniques, which reduce significantly the parasitic emission of CMOS integrated circuits. Both layout level and package-related guidelines are presented. Most of these techniques are being applied successfully in state of the art 0.25 μm CMOS designs
Keywords
CMOS integrated circuits; electromagnetic compatibility; integrated circuit design; integrated circuit packaging; 0.25 micron; CMOS integrated circuits; efficient design techniques; layout level; low emission integrated circuits; package-related guidelines; parasitic emission; CMOS integrated circuits; Electromagnetic compatibility; Electronics packaging; Fluctuations; Foundries; Guidelines; Integrated circuit packaging; MOS devices; Semiconductor device measurement; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Devices, Circuits and Systems, 2000. Proceedings of the 2000 Third IEEE International Caracas Conference on
Conference_Location
Cancun
Print_ISBN
0-7803-5766-3
Type
conf
DOI
10.1109/ICCDCS.2000.869805
Filename
869805
Link To Document