Optimisation of 100V high side LDMOS using multiple simulation techniques

Author

Elwin, M. ; Holland, P. ; Anteney, I. ; Ellis, J. ; Armstrong, L. ; Birchby, G. ; Igic, P.

Author_Institution

Dept. of Sch. of Eng., Swansea Univ., Swansea, UK

fYear

2009

fDate

14-18 June 2009

Firstpage

104

Lastpage

107

Abstract

A combination of conventional cross sectional process and device simulations combined with top down and 3D device simulations have been used to design and optimise the integration of a 100 V Lateral DMOS (LDMOS) device for high side bridge applications. This combined simulation approach can streamline the device design process and gain important information about end effects which are lost from 2D cross sectional simulations. Design solutions to negate detrimental end effects are proposed and optimised by top down and 3D simulations and subsequently proven on tested silicon.

Keywords

MOS integrated circuits; optimisation; 3D device simulations; cross sectional process; lateral DMOS device; side bridge applications; silicon; voltage 100 V; Breakdown voltage; CMOS technology; Design optimization; Electrostatics; Integrated circuit manufacture; Manufacturing processes; Power integrated circuits; Power transistors; Silicon; Substrates;

fLanguage

English

Publisher

ieee

Conference_Titel

Power Semiconductor Devices & IC's, 2009. ISPSD 2009. 21st International Symposium on

Conference_Location

Barcelona

ISSN

1943-653X

Print_ISBN

978-1-4244-3525-8

Electronic_ISBN

1943-653X

Type

conf

DOI

10.1109/ISPSD.2009.5158012

Filename

5158012