Control-Flow Checking Using Branch Instructions

This paper presents a hardware control-flow checking scheme for RISC processor-based systems. This scheme combines two error detection mechanisms to provide high coverage. The first mechanism uses parity bits to detect faults occurring in the opcodes and in the target addresses of branch instructions which lead to erroneous branches. The second mechanism uses signature monitoring to detect errors occurring in the sequential instructions. The scheme is implemented using a watchdog processor for an VHDL model of the LEON2 processor. About 31800 simulation faults were injected into the LEON2 processor. The results show that the error detection coverage is about 99.5% with average detection latency of 7 cycles. The performance loss of presented scheme is about 8.4%.