Trends in low power digital system-on-chip designs

A study of the future trends in low-power System-on-Chip (SoC) designs is presented, based on the recently announced ITRS-2001 technology characteristics for both high-performance and low-power devices from 2001 to 2016. We forecast the logic/memory composition of a reference low-power PDA design with an area constraint of 1 cm² using both a bottom-up, power dissipation-constrained chip model and a top-down, design resource-constrained model. Together, these analyses indicate that without accelerated improvements in both chip design productivity and leakage power management, future SoC designs will be comprised of 80-90% memory, with the remaining logic blocks composed of special-purpose reusable IP cores, and a smaller fraction of the chip containing newly designed logic.