DocumentCode
2429758
Title
On the relation between SAT and BDDs for equivalence checking
Author
Reda, Sherief ; Drechsler, Rolf ; Orailoglu, Alex
Author_Institution
Dept. of Comput. Sci. & Eng., California Univ., San Diego, La Jolla, CA, USA
fYear
2002
fDate
2002
Firstpage
394
Lastpage
399
Abstract
State-of-the-art verification tools are based on efficient operations on Boolean formulas. Traditional manipulation techniques are based on binary decision diagrams (BDDs) and SAT (Boolean satisfiability) solvers. In this paper, we study the relation between the two procedures and show how the number of backtracks obtained in the Davis-Putnam (DP) procedure is linked to the number of paths in the BDD. We utilize this relation to devise a method that uses BDD variable ordering techniques to run the DP procedure. Experimental results confirm that the proposed method results in a dramatic decrease in the number of backtracks and in the time needed to prove the Boolean satisfiability problem as well.
Keywords
Boolean algebra; backtracking; binary decision diagrams; circuit CAD; computability; equivalent circuits; integrated circuit design; logic CAD; logic design; BDD paths; BDD variable ordering; Boolean formulas; Boolean operations; Boolean satisfiability problem; DP procedure; Davis-Putnam procedure; SAT solvers; backtracks; binary decision diagrams; equivalence checking; verification tools; Art; Automatic test pattern generation; Binary decision diagrams; Boolean functions; Circuits; Computer science; Data structures; Decision trees;
fLanguage
English
Publisher
ieee
Conference_Titel
Quality Electronic Design, 2002. Proceedings. International Symposium on
Print_ISBN
0-7695-1561-4
Type
conf
DOI
10.1109/ISQED.2002.996778
Filename
996778
Link To Document