• DocumentCode
    242980
  • Title

    Implementation of vedic multiplier technique on multicore processor

  • Author

    Tuwanuti, Panwit ; Thongbai, Nopphagaw

  • Author_Institution
    Fac. of Inf. Technol., King Mongkut´s Inst. of Technol. Ladkrabang, Bangkok, Thailand
  • fYear
    2014
  • fDate
    22-25 Oct. 2014
  • Firstpage
    1
  • Lastpage
    6
  • Abstract
    This article describes about the mathematic parallel process idea by using Vedic Multiplier techniques. Vedic mathematics is an ancient India that one type of quick trick for calculating that most popular and worldwide acceptation in tutor school. Vedic can apply to use in information technology, science field. They have many researches that used apply Vedic mathematics to accelerate effective of computation. In this paper using Urdhva Tiyakbhyam Sutra and Nikhilam Sutra with both to implement on Multi core processing with MPICH2 (MPI protocol). Urdhva Tiyakbhyam Sutra uses to splitting long digits to sub block for distributing to some other core. Nikhilam Sutra is used for reduce value to improve some of computation effectively.
  • Keywords
    multiprocessing systems; MPI protocol; MPICH2; Vedic mathematics; Vedic multiplier technique; information technology; mathematic parallel process; multicore processing; multicore processor; tutor school; Arrays; Finishing; Hardware; Information technology; Libraries; Mathematics; Standards; MPI implementation; Parallel Multiplier; Vedic Multiplier;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    TENCON 2014 - 2014 IEEE Region 10 Conference
  • Conference_Location
    Bangkok
  • ISSN
    2159-3442
  • Print_ISBN
    978-1-4799-4076-9
  • Type

    conf

  • DOI
    10.1109/TENCON.2014.7022325
  • Filename
    7022325