A novel architecture for dynamic integral image generation for Haar-based face detection on FPGA

Integral Image generation is an important step in the Haar-based face detection algorithm and plays a vital role in the optimization of the algorithm for real-time implementation by evaluating each of the thousands of Haar-features in constant time. The integral image of a frame needs to be generated as a pre-processing stage before running the Haar-classifier on the detection windows within the frame. The delay required in the pre-processing stage is directly proportional to the resolution of the frame and becomes substantial with increasing resolution, limiting the real-time operation of the entire algorithm. This paper presents a novel architecture for generating the integral images of the current detection window dynamically, such that the pre-processing delay is reduced substantially. It is shown that an improvement of 13.71 times is obtained for VGA frames by this approach. The usage of hardware resources is also reduced by around 50% compared to previous implementations.