DocumentCode
2430217
Title
Timing and design closure in physical design flows
Author
Coudert, Olivier
Author_Institution
Monterey Design Syst., Sunnyvale, CA, USA
fYear
2002
fDate
2002
Firstpage
511
Lastpage
516
Abstract
A physical design flow consists of producing a production-worthy layout from a gate-level netlist subject to a set of constraints. This paper focuses on the problems imposed by shrinking process technologies. It exposes the problems of timing closure, signal integrity, design variable dependencies, clock and power/ground routing, and design signoff. It also surveys some physical design flows, and outlines a refinement-based flow.
Keywords
capacitance; circuit optimisation; crosstalk; delays; integrated circuit design; logic CAD; network routing; network topology; timing; constraints; design closure; design signoff; design variable dependencies; gate-level netlist; physical design flows; power/ground routing; process technologies; refinement-based flow; signal integrity; timing; Capacitance; Clocks; Crosstalk; Delay estimation; Logic; Routing; Signal design; Signal synthesis; Timing; Wire;
fLanguage
English
Publisher
ieee
Conference_Titel
Quality Electronic Design, 2002. Proceedings. International Symposium on
Print_ISBN
0-7695-1561-4
Type
conf
DOI
10.1109/ISQED.2002.996796
Filename
996796
Link To Document