DocumentCode
2430273
Title
Hierarchical front-end physical design solution drives modified hand-off
Author
Dai, Wei-Jin ; Courtoy, Michel
fYear
2002
fDate
2002
Firstpage
529
Lastpage
533
Abstract
A design methodology for the implementation of multimillion gate system-on-chip designs is described The new methodology is based on the creation of a physical prototype early in the back-end design process. The prototype is generated in a fraction of the time required to complete the traditional back-end flow but still maintains very high correlation with the final design. The physical prototype becomes the ´hub´ where many design implementation decisions can be optimized by leveraging the short iteration times. Hierarchical design methodologies benefit from the prototyping stage by enabling a more optimal partitioning. The physical prototype also alters the nature of the hand-off model between front-end and back-end designers. The netlist can now be quickly validated using the prototype: the physical reality is being injected early in the design process resulting in fewer iterations between front-end and back-end.
Keywords
application specific integrated circuits; circuit layout CAD; integrated circuit layout; integrated circuit modelling; iterative methods; logic CAD; network topology; back-end design process; design implementation decisions; design methodology; hand-off model; hierarchical front-end physical design solution; iteration times; iterations; multimillion gate system-on-chip designs; netlist; physical reality; prototyping stage; Design methodology; Design optimization; Geometry; Logic design; Process design; Prototypes; Registers; Silicon; System-on-a-chip; Timing;
fLanguage
English
Publisher
ieee
Conference_Titel
Quality Electronic Design, 2002. Proceedings. International Symposium on
Print_ISBN
0-7695-1561-4
Type
conf
DOI
10.1109/ISQED.2002.996799
Filename
996799
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