Novel structures of 3.3kV 4H-SiC BJTs to reduce the Stacking Faults expansion

Author

Brosselard, P. ; Tournier, D. ; Banu, V. ; Jordá, X. ; Godignon, P. ; Millan, James ; Bano, E.

Author_Institution

Lab. AMPERE INSA Lyon, Villeurbanne, France

fYear

2009

fDate

14-18 June 2009

Firstpage

275

Lastpage

278

Abstract

4H-SiC BJTs have been manufactured on a Norstel epitaxied N⁺/P/N^-/N⁺ substrate with a combination of mesa and JTE as edge termination. A breakdown voltage of 3.3 kV has been measured at 1 muA regardless the active area (0.16 and 1.4 mm²). A current gain of 20 was extracted at 10 V-25degC. 70% of the BJTs did not exhibit a current shift, after a 50 hours DC-stress (25degC).

Keywords

power bipolar transistors; semiconductor device breakdown; silicon compounds; stacking faults; wide band gap semiconductors; BJTs; DC stress; Norstel epitaxied N⁺-P-N^--N⁺ substrate; SiC; bipolar junction transistor; breakdown voltage; current 1 muA; current gain; edge mesa termination; stacking faults; temperature 25 degC; time 50 hour; voltage 10 V; voltage 3.3 kV; wide band gap semiconductors; Contacts; Degradation; Electric resistance; Epitaxial growth; Etching; Silicon carbide; Stacking; Substrates; Temperature; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Power Semiconductor Devices & IC's, 2009. ISPSD 2009. 21st International Symposium on

Conference_Location

Barcelona

ISSN

1943-653X

Print_ISBN

978-1-4244-3525-8

Electronic_ISBN

1943-653X

Type

conf

DOI

10.1109/ISPSD.2009.5158055

Filename

5158055