Design and Analysis of 1-Kb 6T SRAM Using Different Architecture

This paper deals with the design and analysis of 1Kb 6-T Static Random Access Memory (SRAM) at 180nm, focusing on optimizing power and delay. This paper contains two types of architecture to design SRAM, one is bank partitioning architecture and other is matrix array. In memory bank architecture SRAM is divided into 4 blocks with each block having equal capacity of 256b. Memory bank is selected using block selector circuit. The key of low power operation in the SRAM is to reduce the word line capacitance and bit line capacitances. The power dissipation is reduced to 78% in the circuit containing memory bank because in memory bank word line capacitance and bit line capacitance are reduced as only one bank is selected at a time and all the other remain in standby mode at the expense of 6.930% more transistor count. Speed is also improved by 23% in the architecture containing memory bank. Here sense amplifier, bit line conditioning circuit and decoder are also designed and verify various results. All the simulations are performed using IC flow tools at TSMC 180nm technology. The proposed memory circuit has applications in SoC and NoC.