High-Level Power Estimation Model for SOC with FPGA Prototyping

Power consumption reduction has become a first-order requirement for modern IC design, and techniques of high level power estimation are urgently in need for the sake of achieving maximal power reduction with minimal cost by optimizing the design early in the design process. This paper presents a high level power estimation model for system-on-chip (SOC) architectures on FPGA. Working with a system-level SOC synthesis framework, the proposed model takes primary power data as foundation and power estimation is conducted with regard to major event signatures such as bus and memory read/write. Besides, the anomalistic change of LUT numbers in the hardware implementation process is then taken into account, which allows more accurate and efficient power estimation providing invaluable directions for further optimization process. With the proposed model, SOC architectures are designed, and power estimation results of the model are compared with the results from real measurements on a Xilinx Virtex-5 FPGA board.