New design method of low power over current protection circuit for low dropout regulator

In this paper, a low power current protection circuit implemented in LDOs is presented. The proposed circuit, designed in 0.35 mum CMOS process, provides a precise limiting current as well as holding current with low dependency on both supply voltage and regulator output voltage. The experimental results showed the proposed circuit is operable in the regulator output voltage range V_OUT = 1.2 V to V_OUT = 3.6 V and supply voltage range VDD = V_OUT + 0.5 V to VDD = 5.6 V . Since the proposed circuit is composed of few simple basic circuits such as comparator, Schmitt trigger, it has a low current consumption which is less than ISS = 0.82 muA at load current ILOAD = 200 mA. This makes the circuit suitable for low power and low voltage LDO design.