DocumentCode
2431232
Title
On calculation of delay range in fault simulation for test cubes
Author
Kajihara, Seiji ; Oku, Shinji ; Miyase, Kohei ; Wen, Xiaoqing ; Sato, Yasuo
fYear
2009
fDate
28-30 April 2009
Firstpage
64
Lastpage
67
Abstract
This paper proposes a method to compute delay values in 3-valued fault simulation for test cubes which are test patterns with Xs. Because the detectable delay size of each fault by a test cube is fixed after assigning logic values to the Xs in the test cube, the proposed method computes a range of the delay values of the test patterns covered by the test cube. By using the proposed method, we can derive the lowest test quality and the highest test quality of test patterns covered by the test cube.
Keywords
automatic test pattern generation; delays; fault simulation; logic testing; delay range; fault simulation; test cubes; Circuit faults; Circuit simulation; Circuit testing; Computational modeling; Delay effects; Fault detection; Filling; Logic testing; Sequential analysis; Sequential circuits;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Design, Automation and Test, 2009. VLSI-DAT '09. International Symposium on
Conference_Location
Hsinchu
Print_ISBN
978-1-4244-2781-9
Electronic_ISBN
978-1-4244-2782-6
Type
conf
DOI
10.1109/VDAT.2009.5158096
Filename
5158096
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