Title :
Fault-tolerant router with built-in self-test/self-diagnosis and fault-isolation circuits for 2D-mesh based chip multiprocessor systems
Author :
Lin, Shu-Yen ; Shen, Wen-Chung ; Hsu, Chan-Cheng ; Chao, Chih-Hao ; Wu, An-Yeu Andy
Author_Institution :
Grad. Inst. of Electron. Eng., Nat. Taiwan Univ., Taipei, Taiwan
Abstract :
A fault-tolerant router design (20-path router) is proposed to reduce the impacts of faulty routers for 2D-mesh based chip multiprocessor systems. In our experiments, the OCNs using 20PRs can reduce 75.65% ~ 85.01% unreachable packets and 7.78% ~ 26.59% latency in comparison with the OCNs using generic XY routers.
Keywords :
built-in self test; fault tolerance; multiprocessing systems; network-on-chip; 2D-mesh; built-in self-diagnosis; built-in self-test; chip multiprocessor systems; fault-isolation circuits; fault-tolerant router; on-chip networks; Built-in self-test; CMOS technology; Circuit faults; Circuit testing; Delay; Electrical fault detection; Fault detection; Fault tolerant systems; Integrated circuit interconnections; Multiprocessing systems;
Conference_Titel :
VLSI Design, Automation and Test, 2009. VLSI-DAT '09. International Symposium on
Conference_Location :
Hsinchu
Print_ISBN :
978-1-4244-2781-9
Electronic_ISBN :
978-1-4244-2782-6
DOI :
10.1109/VDAT.2009.5158098
