Theoretical investigation of the ultrathin Si-SiO/sub 2/ heterojunction and the role of nitrogen at the Si-SiO/sub 2/ interface

The International Technology Road Map for Semiconductors states that the usual scaling of CMOS devices will stop about the year 2012. The main reason for this is not the lithography scaling problems as was previously thought, but rather the leakage through the silicon dioxide gate with a thickness below 4 nm. The modification of the oxide layer to improve the dielectric constant coupled with the understanding of the microscopic nature of the leakage may extend the current materials technology for a few device generations, before we will ultimately have to switch to a high-k gate dielectric.