Title :
Parallel hardware architecture and FPGA implementation of a differential evolution algorithm
Author :
Jewajinda, Yutana
Author_Institution :
Sch. of Eng. & Ind. Technol., Dept. of Electr. Eng., Silpakorn Univ., Nakornpathom, Thailand
Abstract :
This paper presents a parallel hardware architecture and FPGA implementation of a differential evolution (DE) algorithm. Due to inherently parallelism in DE algorithms, parallel hardware implementation can provide speed up over traditionally software implementation. The performance evaluation is performed by comparing execution time between the proposed FPGA implementation and sequential software implementations on multi-core processors.
Keywords :
evolutionary computation; field programmable gate arrays; mathematics computing; multiprocessing systems; parallel architectures; DE algorithm; FPGA implementation; differential evolution algorithm; field programmable gate array; multicore processor; parallel hardware architecture; parallel hardware implementation; software implementation; FPGA; differential evolution; hardware;
Conference_Titel :
TENCON 2014 - 2014 IEEE Region 10 Conference
Conference_Location :
Bangkok
Print_ISBN :
978-1-4799-4076-9
DOI :
10.1109/TENCON.2014.7022429
