Effective parameterization for IP re-use

The advancement of fabrication technology has doubled the silicon capacity every 18 months. Furthermore, design companies are trying to plug in advance and complex design on a system-on-a-chip (SoC). Yet, the time to implement such a complex design is very long. As a result, this widens the gap between silicon capacity and design productivity. In order to solve the productivity gap problem, this research is introducing a parameterized intellectual property (IP) reuse methodology framework in SoC design. This methodology improves the productivity, design quality and time-to-market of SoC design. The proposed methodology was tested using programmable interval timer (PIT). The results not only show this methodology has successfully reduced the entire IP power consumption and area utilization by 41.74% and 2.42% respectively, but also increase IP´s portability, reusability.