DocumentCode :
243254
Title :
An ultra low-voltage standard cell library in 65-nm CMOS process technology
Author :
Peje, Joseph Leandro B. ; Ho, Hani Herbert L. ; Barot, Floro ; Bautista, Maria Fe G. ; Misagal, Carl Christian E. ; Hizon, John Richard E. ; Alarcon, Louis P.
Author_Institution :
Microelectron. & Microprocessors Lab., Univ. of the Philippines - Diliman, Quezon City, Philippines
fYear :
2014
fDate :
22-25 Oct. 2014
Firstpage :
1
Lastpage :
6
Abstract :
In this paper, the design of an ultra-low voltage standard cell library is discussed. This includes the design constraints in designing each gate on a schematic level as well as techniques used in designing the layout. The method of performing timing and power characterization of the standard cell library and how the logical and physical library files are generated are discussed. The accuracy of the standard cell library is then verified through the use of several test circuits.
Keywords :
CMOS integrated circuits; integrated circuit design; low-power electronics; CMOS process technology; physical library files; power characterization; size 65 nm; test circuits; timing characterization; ultra low-voltage standard cell library; Decision support systems; low-power; sensor platform; standard cell library; subthreshold;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
TENCON 2014 - 2014 IEEE Region 10 Conference
Conference_Location :
Bangkok
ISSN :
2159-3442
Print_ISBN :
978-1-4799-4076-9
Type :
conf
DOI :
10.1109/TENCON.2014.7022443
Filename :
7022443
Link To Document :
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