Low power CMOS charge sharing dynamic latch comparator using 0.18μm technology

This paper discusses the design and analysis of a latching comparator using charge sharing circuit topology for low power and high speed. This topology combines the good features of the resistive dividing comparator and the differential current sensing comparator. This design will be focusing on the minimization of propagation delay and the power dissipation of the comparator, which will improves the comparator performance. Simulation results have been obtained using 0.18μm technology, for a 100 MHz clocked comparator, considering 1.8V supply voltage and 1.8V input range. Design has been carried out in SILVACO EDA tool, the schematic simulations are using Gateway SILVACO EDA tool and layout simulations are verified using Expert SILVACO EDA tool.