DocumentCode
2432603
Title
A gm /ID-based synthesis tool for pipelined analog to digital converters
Author
Shyu, Ya-Ting ; Lin, Cheng-Wu ; Lin, Jin-Fu ; Chang, Soon-Jyh
Author_Institution
Dept. of Electr. Eng., Nat. Cheng-Kung Univ., Tainan, Taiwan
fYear
2009
fDate
28-30 April 2009
Firstpage
299
Lastpage
302
Abstract
This paper presents a circuit-level synthesis tool for pipelined ADCs by consulting the circuit-design experience. A top-down systematic design procedure for a conventional pipelined ADC is summarized. In order to decrease the design period for analog circuit sizing, a design automation methodology based on gm/ID concept is manipulated in the synthesis process. With the proposed design automation flow for pipelined ADCs, the developed synthesis tool can produce satisfactory circuit performance within reasonable simulation time.
Keywords
analogue-digital conversion; electronic design automation; integrated circuit design; pipeline arithmetic; analog circuit sizing; circuit-design experience; circuit-level synthesis tool; design automation methodology; gm/ID-based synthesis tool; pipelined ADC; pipelined analog to digital converters; satisfactory circuit performance; top-down systematic design procedure; Analog integrated circuits; Analog-digital conversion; Analytical models; Circuit simulation; Circuit synthesis; Design automation; Design methodology; Design optimization; Operational amplifiers; Wireless LAN;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Design, Automation and Test, 2009. VLSI-DAT '09. International Symposium on
Conference_Location
Hsinchu
Print_ISBN
978-1-4244-2781-9
Electronic_ISBN
978-1-4244-2782-6
Type
conf
DOI
10.1109/VDAT.2009.5158154
Filename
5158154
Link To Document