A new arbitration circuit for synchronous multiple bus multiprocessor systems

A novel design for an M-user B-server arbiter for a multiple bus system is presented. The arbitration circuit maintains fairness when it is used in a low-order interleaved memory system. The arbiter is also fair for a general-purpose multiprocessor system where the memory modules are uniformly accessed by the processors. The arbitration time grows at a rate O(log₂ M), where M is the number of memory modules in a system. When a system has more than four memory modules, both the gate count and delay of the present design are less than those of previous designs